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    • 专利摘要:
    A digital delay lock loop includes first and second digitally controllable delay lines (202B, 204B) coupled in series therebetween, each comprising an upstream portion (214, 218) and a downstream portion ( 216, 220), the first digitally controllable delay line receiving a reference synchronization signal (TREF) and the second digitally controllable delay line providing a delayed synchronization signal (TREF '); and a digital time converter (212) arranged to evaluate a phase difference between the reference signal (TREF) and the delayed synchronization signal (TREF ') and to generate a first control signal (DLEAD_ [0: n ]) to control the upstream portions (214, 218) or a second control signal (DLAG [0: n]) to control the downstream portions (216, 220) based on the sign and magnitude of the difference in phase.
    公开号:FR3076128A1
    申请号:FR1763220
    申请日:2017-12-26
    公开日:2019-06-28
    发明作者:Shanthi SUDALAIYANDI；Gilles Masson；Michael Pelissier；Mykhailo ZARUDNIEV
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    DIGITAL DELAY LOCK LOOP
    Field of the invention
    The present description relates to the field of synchronization signal generators such as clock generators, and more particularly delay locked loops.
    Presentation of the prior art
    Delay locked loops (DLLs) are widely used for clock generation and synchronization as an alternative to other forms of synchronization generators, such as phase locked loops (PLL). A DLL allows to phase the significant synchronization edges of the synchronization signal. DLLs generally include a delay line having adjustable delay elements for delaying a reference synchronization signal, and a phase detector which determines the phase difference between the reference synchronization signal and the delayed reference signal. A control circuit is then used to convert this phase difference into appropriate control signals to adjust the delay line.
    DLLs have advantages over PLLs due to better jitter performance, since phase errors are not accumulated in noisy environments.
    It has already been proposed to produce fully digital DLLs which offer the advantage of benefiting from the dimensioning of the CMOS technology, allowing a reduced chip surface, a reduced energy consumption and an ease to migrate towards future refinements of advanced CMOS processes. . However, fully digital DLLs generally lead to great design complexity, and thus to relatively high circuit area and power consumption.
    There is therefore a need in the art for a fully digital DLL offering relatively low complexity, low chip area and low energy consumption. summary
    An object of embodiments of the present description is to at least partially solve one or more problems of the prior art.
    In one aspect, a digital delay lock loop is provided comprising: first and second digitally controllable delay lines coupled in series with each other, each comprising an upstream portion and a downstream portion, the first delay line controllably digital receiving a reference synchronization signal and the second delay line controllable digitally providing a delayed synchronization signal; and a time-to-digital converter arranged to evaluate a phase difference between the reference signal and the delayed synchronization signal and to generate a first control signal to control the upstream portions or a second control signal to control the downstream portions based on the sign and the magnitude of the phase difference.
    According to one embodiment, the upstream portions of the first and second digitally controllable delay lines each include a plurality of delay elements, and the time to digital converter comprises a corresponding first plurality of delay elements; and the downstream portions of the first and second digitally controllable delay lines each include a plurality of delay elements, and the time to digital converter comprises a corresponding second plurality of delay elements.
    According to one embodiment, each of the plurality of delay elements of the upstream portions is implemented by a circuit similar to that implementing each delay element of the first plurality, and each of the plurality of delay elements downstream portions is implemented by a circuit similar to that implementing each delay element of the second plurality.
    According to one embodiment, the time to digital converter further comprises a selector circuit arranged to generate: a first pair of synchronization signals if the phase of the reference signal exceeds that of the delayed synchronization signal, a first signal of the first pair comprising a synchronization edge which precedes a synchronization edge of a second signal of the first pair of said phase difference; and a second pair of synchronization signals if the phase of the reference signal follows that of the delayed synchronization signal, a first signal of the second pair comprising a synchronization edge which precedes a synchronization edge of a second signal of the second pair of said phase difference.
    According to one embodiment, the time converter to digital values comprises: an upstream converter of time to digital values comprising a first delay line consisting of a first plurality of delay elements each having an output coupled to an input of l '' a corresponding one of a first plurality of flip-flops, the first signal of the first pair of synchronization signals being supplied to an input of the first delay line, and the first plurality of flip-flops receiving as clock the second signal of the first pair synchronization signals; and a downstream converter of time into digital values comprising a second delay line consisting of a second plurality of delay elements each having an output coupled to an input of a corresponding one of a second plurality of flip-flops, the first signal of the second pair of synchronization signals being supplied to an input of the second delay line, and the second plurality of flip-flops receiving as clock the second signal of the second pair of synchronization signals.
    According to one embodiment, the first plurality of flip-flops is arranged to generate a first digital signal represented by a thermometric code, the time converter into digital values further comprising a first decoder arranged to code the first digital signal on the basis of one-hot coding; and the second plurality of flip-flops is arranged to generate a second digital signal represented by a thermometric code, the time converter into digital values further comprising a second decoder arranged to code the second digital signal on the basis of one-hot coding .
    According to one embodiment, the time converter to digital values further comprises an inverter for reversing the delayed synchronization signal.
    In another aspect, a method for controlling a digital delay locked loop is provided, comprising: evaluating a phase difference between the reference signal and a delayed synchronization signal generated by first and second controllable delay lines of digitally coupled in series with each other, each comprising an upstream portion and a downstream portion, the first digitally controllable delay line receiving a reference synchronization signal and the second digitally controllable delay line providing a delayed synchronization signal ; generating a first control signal to control the upstream portions or a second control signal to control the downstream portions based on the sign and the magnitude of the phase difference.
    According to one embodiment, the method further comprises the generation of: a first pair of synchronization signals if the phase of the reference signal exceeds that of the delayed synchronization signal, a first signal of the first pair comprising a synchronization edge which is ahead of a synchronization edge of a second signal of the first pair of said phase difference; and of a second pair of synchronization signals if the phase of the reference signal follows that of the delayed synchronization signal, a first signal of the second pair comprising a synchronization edge which precedes a synchronization edge of a second signal of the second pair of said phase difference.
    Brief description of the drawings
    The aforementioned characteristics and advantages and others will appear clearly with the following detailed description of embodiments, given by way of illustration and not by limitation, with reference to the accompanying drawings in which: FIG. 1 schematically illustrates a typical example of delay lock loop; FIG. 2 schematically illustrates a digital delay locking loop according to an exemplary embodiment of the present description; FIG. 3A schematically illustrates a TDC controller of the DLL of FIG. 2 in more detail according to an exemplary embodiment; Figures 3B and 3C are timing diagrams showing the operation of a selector circuit of Figure 3A according to an exemplary embodiment; Figure 3D schematically illustrates a phase detector of the DLL of Figure 2 in more detail according to an exemplary embodiment; Figure 4 schematically illustrates the selector circuit of Figure 3A in more detail according to an exemplary embodiment; FIG. 5 schematically illustrates time converters to digital value, decoders and digitally controllable delay lines of the DLL of FIG. 2 in more detail according to an exemplary embodiment; FIGS. 6A and 6B are timing diagrams illustrating an example of signals in the DLL of FIG. 2 according to an exemplary embodiment; FIGS. 7A and 7B represent diagrams of coding of delay line control signals according to an exemplary embodiment; Figures 8A and 8B schematically illustrate DCDLs of Figure 5 in more detail according to an exemplary embodiment; FIG. 9 schematically illustrates delay controllers and digitally controllable delay lines of the DLL of FIG. 2 in more detail according to an example of an alternative to FIG. 5; FIG. 10 illustrates a DLL according to another exemplary embodiment; and FIG. 11 schematically illustrates a DLL according to yet another exemplary embodiment.
    detailed description
    In the present description, the term "connected" is used to designate a direct connection between elements of a circuit, while the term "coupled" is used to designate a connection between elements which can be direct, or which can be do this through one or more intermediate elements like buffers, capacitors, etc.
    Figure 1 illustrates a typical example of a DLL 100. A TREF reference signal is supplied to digitally controllable delay lines (DCDLs) 102 to generate the delayed TREF 'version of the reference signal. The reference signal TREF and the delayed signal TREF 'are supplied to a control circuit 104, comprising a phase detector (PD) 106 and a controller (CONTROLLER) 108. The phase detector 106 compares the phases of the signals TREF and TREF ', and provides output signals to controller 108. Controller 108 generates appropriate digital control signals on output lines 110 to digitally controllable delay lines 102.
    As previously described in the prior art section, there is a technical difficulty in obtaining a circuit having relatively low complexity and chip area to convert a phase difference between the reference signal TREF and the signal of delayed reference TREF 'detected by the phase detector 106 in appropriate digital control signals to control the delay lines 102.
    FIG. 2 schematically illustrates a delay locked loop 200 according to an exemplary embodiment of the present description.
    The DLL 200 comprises a digitally controllable delay line (DCDL1) 202 introducing a delay Tdcdtl, and a digitally controllable delay line (DCDL2) 204 introducing a delay τdcdi2 / the DCDL 202 and 204 being coupled in series with each other . A TREF reference signal is provided on an input line 201 of the DCDL 202. An output line of the DCDL 202 is coupled to an intermediate node 205, which in turn is coupled to an input line of the DCDL 204. The delays τdcdil and rdcdi2 introduced by the DCDL 202 and 204 are for example equal, and are for example chosen so that tdcdii + rdcdl2-T / 2, where T is the period of the reference signal TREF. The signal on the intermediate node 205 thus corresponds to the TREF reference signal delayed by a quarter of period T / 4.
    The output line of the DCDL 204 is coupled to inverter ion 206, which generates on its output ion reverse signal TREF + T / 2. The output of the inverter 206 is coupled to an input of a phase detector (PD) 208, the other input of which is coupled to the input line 201 receiving the reference signal TREF, which in certain cases is delayed , by a delay element 210, of a time rd to compensate for the delay introduced by the inverter 206. The phase detector 208 compares the relative phases of the signals TREF + T / 2 and TREF and generates output signals UP and DN based on the amplitude and the sign of the phase difference between the TREF and TREF + T / 2 signals. The ÜP and DN signals are supplied to a TDC controller (time converter to digital values) (TDC CONTROLLER) 212.
    The TDC 212 controller generates digital adjustment signals DLEAD_ [0: n] and DLAG_ [0: n] on output lines coupled to DCDL 202 and 204. For example, DCDL 202 includes a fixed DCDL (F- DCDL1) 202A, coupled in series with an adjustable DCDL (T-DCDL1) 202B, and the DCDL 204 comprises a fixed DCDL (F-DCDL2) 204A, coupled in series with an adjustable DCDL (T-DCDL2) 204B. The fixed DCDLs 202A, 204A are not adjustable by the TDC controller 212, but in the embodiment of FIG. 2 they are adjustable by control signals TUNE1 and TUNE2 to correct any discrepancy between the DCDL 202 and 204. The TUNE1 and TUNE2 signals are for example generated by an appropriate control circuit (not shown). The adjustable DCDL 202B and 204B each introduce a delay which is adjusted by the digital signals DLEAD_ [0: n] and DLAG_ [0: n) coming from the TDC controller 212. For example, the adjustable DCDL 202B comprises an upstream portion 214 controlled by the signal DLEAD_ [0: n] and a downstream portion 216 controlled by the signal DLAG_ [0: n]. Similarly, the adjustable DCDL 204B comprises for example an upstream portion 218 controlled by the signal DLEAD_ [0: n] and a downstream portion 220 controlled by the signal DLAG_ [0: n].
    The TDC controller 212 is for example deactivated by the low state of an erasure signal CLR generated by an AND gate 222. The AND gate 222 has for example one of its inputs coupled to the output of a starting circuit (I_START) 224, which has an input coupled to the input line 201, and which generates on its output line a START signal which passes to the high state only some time after the departure of the reference signal TREF. This prevents unstable behavior of the control loop until the operation of the DCDL is stabilized. The other input of ET gate 222 is coupled to a LOCK DETECT 226, which in turn has inputs coupled to the output lines of the phase detector 208. The lock detection circuit 226 provides a high signal unless it determines, on the basis of the UP and DN signals from the phase detector 208, that the delay introduced by the DCDL has converged towards the target level, in which case it outputs a low signal which disables the TDC 212 controller.
    FIG. 3A schematically illustrates the TDC controller 212 in more detail according to an exemplary embodiment. The controller 212 comprises for example a selector circuit (SELECTOR) 302, which receives the UP and DN signals from the phase detector 208, and generates four output signals UP_LEAD, DN_LAG, DN_LEAD and UP_LAG. The TDC controller 212 further comprises an upstream TDC circuit (LEAD TDC) 304 and a downstream TDC circuit (LAG TDC) 306. The upstream TDC circuit 304 receives the signals UP_LEAD and DN_LAG, and converts the time information represented by these signals into a digital signal TLEAD_ [0: n]. The downstream TDC circuit · 306 receives the signals DN_LEAD and UP_LAG, and converts the time information represented by these signals into a digital signal TLAG_ [0: n]. In the embodiment of FIG. 3A, the TDC controller 212 further comprises an upstream decoder (LEAD DECODER) 308 and a downstream decoder (LAG DECODER) 310 for converting the digital signals TLEAD_ {0: n], TLAG_ [ 0: n] in digital signals DLEAD_ [0: n], DLAG_ [0: n].
    FIGS. 3B and 3C are timing diagrams representing the generation of the signals UP_LEAD, DN_LAG, DN_LEAD and UP_LAG by the selector circuit 302 of FIG. 3A according to an exemplary embodiment.
    FIG. 3B illustrates an example in which the signal TREF precedes the signal TREF + T / 2 by a phase difference Δφ. In this case, the UP signal is activated first, a fixed time after the rising edge of the TREF signal. The DN signal is activated at a fixed time after the rising edge of the TREF + T / 2 signal. Once the two signals UP and DN are high, they are reset after a minimum logic delay in the phase detector 208. The delay between the rising edges of the signals UP and DN represents an upstream phase error Δφΐ.
    FIG. 3C illustrates an opposite example in which the signal TREF follows behind the signal TREF + T / 2 by a phase difference Δφ. In this case, the DN signal is activated first, at a fixed time after the rising edge of the TREF + T / 2 signal. The UP signal is activated at a fixed time after the rising edge of the TREF signal. Once the two signals UP and DN are high, they are reset after a minimum logic delay in the phase detector 208. The delay between the rising edges of the signals DN and UP represents a downstream phase error Δφ2.
    Thus the selector circuit 302 generates either the UP_LEAD and DN_LAG signals in which the rising edge of the UP_LEAD signal always exceeds the rising edge of the DN_LAG signal of the phase difference, or the UP_LAG and DN_LEAD signals in which the rising edge of the DN_LEAD signal always advances the rising edge of the UP_LAG signal of the phase difference.
    Figure 3D schematically illustrates the phase detector 208 of Figure 2 in more detail according to an exemplary embodiment. It will be clear to those skilled in the art that the circuit of FIG. 3D is only an example of the implementation of the phase detector 208, and that many variants would be possible.
    FIG. 4 schematically illustrates an example of implementation of the selector circuit 302. The selector circuit 302 comprises for example six flip-flops 401 to 406. Flip-flops 401 and 402 receive the UP signal as clock, flip-flop 403 receives the reverse as clock of the UP signal, flip-flops 404 and 405 receive the DN signal as a clock, and flip-flop 406 receives the inverse of the DN signal as clock. The flip-flop 401 has its data input coupled so as to receive the signal DN, and the flip-flop 402 has its data input coupled so as to receive the signal DN after delay ion introduced by a buffer 408. The flip-flop 403 has its data input d coupled to its inverted output q. Similarly, flip-flop 404 has its data input coupled so as to receive the UP signal, and flip-flop 405 has its data input coupled so as to receive the UP signal after a delay introduced by a buffer 410. flip-flop 406 has its data input d coupled to its inverted output.
    The selector circuit 302 further comprises for example six AND gates 411 to 416. The AND gate 411 is an AND gate with 3 inputs having its respective inputs coupled to the outputs q of flip-flops 401 and 402 and to the output of the AND gate 413. The AND gate 412 is also an AND gate with 3 inputs having its respective inputs coupled to the inverted outputs q of the flip-flops 401, 402 and to the output of the AND gate 413. The AND gate 413 has an input coupled to the output of a buffer 418 receiving the UP signal, and its other input coupled to the output q of the flip-flop 403.
    Similarly, the AND gate 414 is an AND gate with 3 inputs having their respective inputs coupled to the outputs q of flip-flops 404 and 405 and at the output of the AND gate 416. The AND gate 415 is also an AND gate with 3 inputs having its respective inputs coupled to the inverted outputs q of flip-flops 404, 405 and to the output of the AND gate 416. The AND gate 416 has an input coupled to the output of a buffer 420 receiving the signal DN, and its other coupled input at the output q of the flip-flop 406.
    The AND gates 411, 412, 414 and 415 respectively supply the UP_LAG, UP_LEAD, DN_LAG and DN_LEAD signals on their outputs.
    FIG. 5 schematically illustrates the upstream and downstream TDCs 304, 306 and the upstream and downstream decoders 308, 310 of the TDC controller 212, and the adjustable DCDLs 202B and 204B, in more detail according to an exemplary embodiment of the present description.
    The upstream TDC 304 comprises for example delay elements 502_0 to 502_n and flip-flops 504_0 to 504_n. Each delay element 502_0 to 502_n comprises for example an input in and an output out, and the delay elements 502_0 to 502_n are for example coupled in series via these inputs and outputs. Each delay element 502_0 to 502_n further comprises, for example, an output nin, a control input c and another input pout, which are all for example connected to a high logic level tie-h. The delay element 502_0 receives for example on its input the signal UP__LEAD. The output of each delay element 502_0 to 502_n is respectively coupled to a data input d of the corresponding flip-flop 504__0 to 504_n. The flip-flops 504_0 to 504_n receive, for example as a clock, the signal DN_LAG. The outputs q of flip-flops 504_0 to 504_n respectively supply the bits TLEAD_0 to TLEAD_n of the digital signal TLEAD_ [0: n] at the output of the upstream TDC 304.
    The upstream decoder 308 comprises for example EXCLUSIVE OR gates 506_0 to 506_n each having one of its inputs coupled to the output of the flip-flop 504_0 to 504_n corresponding, and its other input coupled to the output of the next flip-flop in the chain. The other input of the EXCLUSIVE OR gate 506__n is for example connected to a low logic level tie-1. EXCLUSIVE OR gates 506_0 to 506_n respectively supply the digital signals DLEAD_0 to DLEAD_n.
    As described above, the adjustable DCDL 202B includes the upstream portion (LEAD_DCDL1) 214 and the downstream portion (LAG_DCDL1) 216, and the adjustable DCDL 204B also includes an upstream portion (LEAD_DCDL2) 218 and a downstream portion (LAG_DCDL2) 220 .
    The upstream portions 214 and 218 comprise for example delay elements 508_0 to 508_n and 510_0 to 510_n respectively, each of these delay elements having a control input c coupled so as to receive the corresponding digital signal DLEAD_0 to DLEAD_n. The delay elements 508_0 to 508_n and 510_0 to 510_n each further include in and pout inputs, and out and nin outputs. The delay elements 508_0 to 508_n are for example coupled in series via their out outputs and their pout inputs and also by their nin outputs and their in inputs. Similarly, the delay elements 510_0 to 510_n are for example coupled in series via their out outputs and their pout inputs and also by their nin outputs and their in inputs. The delay elements 508_0 and 510_0 each have for example their output nin coupled to their input pout. The element 508_n has for example its input coupled so as to receive the reference signal TREF "at the output of the fixed DCDL 202Ά of FIG. 2. The output out of the delay element 508_n provides an intermediate signal TREF_1, which is supplied to the downstream portion 216. The delay element 510_n has for example its input in coupled so as to receive the reference signal TREF "at the output of the fixed DCDL 204A of FIG. 2. The output out of the the delay element 510_n provides an intermediate signal TREF_2, which is supplied to the downstream portion 220.
    The downstream TDC 306 comprises for example delay elements 512_0 to 512_n and flip-flops 514_0 to 514_n. Each delay element 512_0 to 512_n comprises for example an input in and an output out, and the delay elements 512_0 to 512_n are, for example, coupled in series via these inputs and outputs. Each delay element 512_0 to 512_n further comprises, for example, an output nin, a control input c and another input pout, which are all for example connected to a high logic level tie-h. The delay element 512_0 receives for example on its input the signal DN_LEAD. The output of each delay element 512_0 to 512_n is respectively coupled to a data input d of the corresponding flip-flop 514_0 to 514_n. The flip-flops 514_0 to 514_n for example receive the UP_LAG signal as a clock. The outputs q of flip-flops 514_0 to 514_n respectively supply the bits TLAG_0 to TLAG_n of the digital signal TLAG_ [0: n] at the output of the downstream TDC 306.
    The downstream decoder 310 comprises, for example, EXCLUSIVE OR gates 516_0 to 516_n each having one of its inputs coupled to the output of the corresponding flip-flop 514__0 to 514_n, and its other input coupled to the output of the preceding flip-flop in the chain. The other input of the EXCLUSIVE OR gate 516_0 is for example connected to a high tie-h logic level. EXCLUSIVE OR gates 516_0 to 516_n respectively supply the digital signals DLAG_0 to DLAG_n.
    The downstream portions 216 and 220 comprise for example delay elements 518_0 to 518_n and 520_0 to 520_n respectively, each of these delay elements having a control input c coupled so as to receive the corresponding digital signal DLAG_0 to DLAG_n. The delay elements 518_0 to 518_n and 520_0 to 520_n each further include in and pout inputs, and out and nin outputs. The delay elements 518_0 to 518_n are for example coupled in series via their out outputs and their pout inputs and also by their nin outputs and their in inputs. Similarly, the delay elements 520_0 to 520_n are for example coupled in series via their out outputs and their pout inputs and also by their nin outputs and their in inputs. The delay elements 518_n and 520_n each have for example their output nin coupled to their input pout. The element 518_0 has for example its input coupled so as to receive the intermediate reference signal TREF_1 at the output of the upstream portion 214. The output out of the delay element 518_0 provides the intermediate signal TREF + T / 4, which is supplied at the entrance of the fixed DCDL 204A. The delay element 520_0 has for example its input coupled so as to receive the intermediate signal TREF_2 at the output of the upstream portion 218. The output out of the delay element 520_0 provides the output signal TREF + T / 2 delay lines.
    We will now describe in more detail the operation of the circuits of Figures 2, 3A and 5 with reference to Figures 6A is 6B.
    FIGS. 6A and 6B are timing diagrams representing examples of the signals TREF, TREF + T / 4, TREF + T / 2, TREF + T / 2, START, UP, DN, UP_LEAD, DN_LAG, TLEAD_ [0: n], DLEAD [0: n], DN_LEAD, UP_LAG, TLAG_ [0: n] and DLAG_ [0: n].
    FIG. 6A illustrates an example in which rising edges of the TREF signal initially precede the rising edges of the TREF + T / 2 signal.
    During the first rising edges 602 and 604 of the reference signal TREF, the signal START generated by the circuit 224 of FIG. 2 is low, and thus the TDC controller 212 is not yet active. Therefore, while the phase detector 208 begins to generate pulses in the UP and DN signals, the output signals from the selector circuit 302 remain low. At an instant t1, the START signal goes high, then at an instant t2, a rising edge following 606 of the reference signal TREF is taken into account by the TDC controller 212. In particular, the signal UP has a rising edge 608 shortly after the rising edge 606. At an instant t3, the signal TREF + T / 2 has a rising edge 610, and the signal DN thus has a rising edge 612 soon after. In view of the fact that the signal UP precedes the signal DN, the signal UP_LEAD has a rising edge 614 shortly after the rising edge 608, and the signal DN_LAG has a rising edge 616 shortly after the rising edge 612. The signals UP, DN, UP_LEAD and DN_LAG all go low at time t4. For example, when the two signals UP and DN are high, they are automatically reset by an AND gate located in the phase detector 208, and the signals UP_LEAD and DN_LAG follow the signals UP and DN respectively.
    The signal TLEAD [0: n] is generated on the basis of the phase difference Δφΐ between the rising edges 614 and 616 of the signals UP_LEAD and DN_LAG respectively, and the signal DLEAD_ [0: n] -is also generated, so that shortly after the rising edge 616 of the signal DN_LAG, the delays introduced by the upstream portions of the DCDL 202B and 204B are reduced. A rising edge along 618 of the TREF reference signal and thus for example aligned with ion rising edge 620 of the TREF + T / 2 signal.
    FIG. 6B illustrates an example in which rising edges of the TREF signal initially follow behind the rising edges of the TREF + T / 2 signal.
    During the first rising edges 622 and 624 of the reference signal TREF, the signal START generated by the circuit 224 of FIG. 2 is low, and thus the TDC controller 212 is not yet active. Therefore, while the phase detector 208 begins to generate pulses in the UP and DN signals, the output signals from the selector circuit 302 remain low. At an instant tl, the START signal goes high, then at an instant t2, a rising edge of the TREF + T / 2 signal is taken into account by the TDC controller 212. In particular, the signal DN has a rising edge 628 shortly after the rising edge 626. At an instant t3, the reference signal TREF has a rising edge 630, and the signal UP thus has a rising edge 632 shortly after. In view of the fact that the signal DN precedes the signal UP, the signal DN_LEAD has a rising edge 634 shortly after the rising edge 628, and the signal UP_LAG has a rising edge 636 shortly after the rising edge 632. The signals UP, DN, DN_LEAD and UP_LAG all go low at time t4.
    The signal TLAG [0: n] is generated on the basis of the phase difference Δφΐ between the rising edges 634 and 636 of the signals DN_LEAD and UP_LAG respectively, and the signal DLAG_ [0: n] is also generated, so that shortly after the rising edge 636 of the UP_LAG signal, the delays introduced by the downstream portions of the DCDL 202B and 204B are increased. A rising edge following 638 of the TREF reference signal is thus for example aligned with a rising edge 640 of the TREF + T / 2 signal.
    FIGS. 7A and 7B represent an example of decoding the thermometric code into one-hot coding as carried out by the decoders 308 and 310 of FIG. 3A. The upstream and downstream TDCs 304 and 306 generate, for example, forms of thermometric coding that are reversed with respect to each other, and the transformation is thus different.
    FIG. 7A represents the thermometric coding generated by the upstream TDC 304 in which the code passes from a value of "000 ... 00” to a value of "111 ... 11" with the values "1" replacing the values "0" from the right. Adding a "0" on the left with the value tie-1 in figure 5 and represented by a block 702 in figure 7A implies that the one-hot coding increments by "000 ... 00 "to" 000 ... 01 "to" 000 ... 10 ", etc. by going up to a value of" 100 ... 00 ".. Thus the upstream portions 214 and 218 of the DCDLs 202B and 204B provide maximum delay when the signal DLEAD_ [0: n] is in the default state of "000 ... 00", and a minimum delay when the signal DLEAD __ [0: n] has reached "100. ..00. "
    FIG. 7B represents the thermometric coding generated by the downstream TDC 306 in which the code progresses in increments from a value of "000 ... 00" to "100 ... 00" to "110 ... 00" etc. going up to a value of "111 ... 11" with the values "1" replacing the values "0" from the left. The addition of a "1" on the left by the value tie-h in figure 5 and represented by a block 704 in figure 7B implies that the one-hot coding increments from a value of "100 ... 00 "to" 010 ... 00 "to" 001 ... 00 "and up to a low value of" 000 ... 00 ". Thus the downstream portions 216 and 220 of the DCDL 202B and 204B provide a minimum delay when the signal DLAG_ [0: n] is in the default state of "100 ... 00", and a maximum delay when the signal DLAG_ [ 0: n] has reached "000 ... 00".
    FIG. 8A schematically illustrates the delay elements 508_Q to 508_n of the upstream portion 214 in more detail according to an exemplary embodiment. The upstream portion 218 is for example implemented in a similar manner, and the delay elements 502_0 to 502_n of the TDC controller 212 are for example implemented by similar circuits.
    Each delay element 508_0 to 508_n comprises for example a NAND gate 802 having an input coupled to the input in of the delay element, and its other input receiving the control signal c_n inverted by an inverter 804. The output of the NAND gate 802 provides the nin output of the delay element.
    Each delay element further comprises a NAND gate 806 having an input coupled to the input in, and its other input coupled so as to receive the control signal c_n. The output of the NAND gate 806 is coupled to an input of another NAND gate 808, which has its other input coupled to the input pout of the delay element. NAND gate 808 has its output coupled to the output of the delay element. In certain embodiments a dummy NAND gate (D) is coupled to the output of the NAND gate 806 for the purpose of load adaptation.
    FIG. 8B schematically illustrates the delay elements 518_0 to 518_n of the downstream portion 216 of the DCDL 202B in more detail according to an exemplary embodiment. The delay elements are implemented by the same circuit as the delay elements 508_0 to 508_n, and this circuit will not be described again in detail. In certain embodiments, the value of c_n of the final cell DCDE (n) is coupled to the high logic level tie-h in order to maintain default states.
    FIG. 9 schematically illustrates the upstream and downstream TDCs 304, 306 and the adjustable DCDLs 202B and 204B, in more detail according to another exemplary embodiment similar to that of FIG. 5, but in which the. upstream and downstream decoders 308, 310 of the TDC controller 212 have been omitted. Indeed, the signals TLEAD_0 to TLEAD_n generated by the outputs q of the flip-flops 504_0 to 504_n are directly coupled to the control inputs c of the delay elements 508_0 to 508__n and 510_0 to 510_n. The default state of maximum delay is still maintained when the signals on the inputs of the flip-flops and therefore the signals TLEAD_0 to TLEAD_n are all at "0".
    However, the signals TLAG_0 to TLAG_n are for example generated by the outputs q of the flip-flops 514_0 to 514_n so that the default state of minimum delay can be applied when the signals on the inputs of the flip-flops are at "0".
    An advantage of removing decoders 308, 310 is that it simplifies the controller, reduces the chip area and leads to reduced power consumption.
    FIG. 10 schematically illustrates a digital DLL 1000 according to another exemplary embodiment. Many elements of DLL 1000 are similar to elements of DLL 200 of FIG. 2, and these elements have the same reference numbers and will not be described again in detail.
    In DLL 1000 of Figure 10, rather than having two DCDLs which when adjusted introduce a total delay of half a period, there are four DCDLs 1002, 1004, 1006 and 1008 which when they are adjusted introduce a total delay equal to an entire period of the TREF reference signal. Each DCDL 1002 to 1008 comprises for example a fixed DCDL 1002A, 1004A, 1006A and 1008A respectively, and an adjustable DCDL 1002B, 1004B, 1006B and 1008B respectively. In addition, the adjustable DCDL 1002B comprises for example an upstream portion 1010 and a downstream portion 1012, the adjustable DCDL 1004B comprises for example an upstream portion 1014 and a downstream portion 1016, the adjustable DCDL 1006B comprises for example an upstream portion 1018 and a downstream portion 1020, and the adjustable DCDL 1008B comprises for example an upstream portion 1022 and a downstream portion 1024. The upstream portions 1010, 1014, 1018 and 1022 are for example controlled by the signal DLEAD_ [0: n] generated by the controller. TDC 212, and the downstream portions 1012, 1016, 1020 and 1024 are for example controlled by the signal DLAG_ [0: n]. The nodes 1026, 1028 and 1030 between the DCDLs 1002, 1004, 1006 and 1008 respectively provide signals PHASE1, PHASE2 and PHASE3 respectively corresponding respectively to the signal TREF + T / 4, to the signal TREF + T / 2, and to the signal TREF + 3T / 4.
    FIG. 11 schematically illustrates a digital DLL 1100 according to yet another exemplary embodiment. Many elements of the DLL 1100 are similar to elements of the DLL 200 of FIG. 2, and these elements have the same reference numbers and will not be described again in detail.
    As in DLL 1000 of Figure 10, in DLL 1100 of Figure 11, digitally controllable delay lines introduce, when adjusted, a total delay equal to a full period of the TREF reference signal.
    In the example of figure 11, there is a delay line on the left side L comprising a fixed DCDL (3F-DCDL1) 1102 which can be calibrated by the adjustment signal TUNE1, and which is for example capable of introduce three times the delay of the other DCDLs, and an adjustable portion 1103 comprising three adjustable DCDLs (T_DCDL1) 1104, 1106 and 1108. There is also a delay line on the right side R comprising a fixed DCDL (F_DCDL2) 1110 which can be calibrated by the adjustment signal TUNE2, and an adjustable portion (T-DCDL2) 1112. Each of the adjustable portions 1104, 1106, 1108 and 1112 comprises for example an upstream portion controlled by the signal DLEAD_ [0: n] generated by the TDC controller 212, and a downstream portion controlled by the DLAG_ [0: n] signal generated by the TDC controller 212. An intermediate node 1114 between the delay lines on the left and right side, L and R, can provide a signal having a customizable phase, for example corresponds ant to TREF + nL / (nL + nR), where nL is the number of delay elements in the left delay line L, and nR is the number of delay elements in the right delay line R.
    An advantage of the embodiments described here is that a DLL can be implemented in a fully digital solution in a relatively simple manner, and while using only standard cells which can for example be implemented using CMOS technology.
    With the description thus made of at least one illustrative embodiment, various alterations, modifications and improvements will readily appear to those skilled in the art. For example, although examples of circuits implementing the selector circuit and delay elements have been described, it will be clear to a person skilled in the art that variants of implementation would be possible.
    In addition, in certain embodiments the flip-flops 504_0 to 504_n in the upstream TDC 304 and / or the flip-flops 514_0 to 514_n in the downstream TDC 306 could be replaced by synchronization flip-flops. For example, each flip-flop is replaced by a pair of synchronization flip-flops coupled in series and both receiving as clock the signal DN_LAG in the case of flip-flops of the upstream TDC 304, or the signal UP_LAG in the case of flip-flops of the downstream TDC 306 The phase error estimation and the phase error correction would then be carried out on two clock cycles, for example two rising edges.
    权利要求:
    Claims (9)
    [1" id="c-fr-0001]
    1. Digital delay lock loop comprising: first and second digitally controllable delay lines (202B, 204B) coupled in series with each other, each comprising an upstream portion (214, 218) and a downstream portion (216, 220 ), the first digitally controllable delay line receiving a reference synchronization signal (TREF) and the second digitally controllable delay line providing a delayed synchronization signal (TREF '); and a time to digital converter (212) arranged to evaluate a phase difference between the reference signal (TREF) and the delayed synchronization signal (TREF ') and to generate a first control signal (DLEAD __ [0: n ]) to control the upstream portions (214, 218) or a second control signal (DLAG [0: n]) to control the downstream portions (216, 220) based on the sign and the magnitude of the difference phase.
    [2" id="c-fr-0002]
    2. A digital delay lock loop according to claim 1, wherein: the upstream portions (214, 218) of the first and second digitally controllable delay lines (202B, 204B) each include a plurality of delay elements ( 508_0 to 508_n, 510_0 to 510_n), and the time to digital converter (212) includes a first corresponding plurality of delay elements (502_0 to 502_n); and the downstream portions (216, 220) of the first and second digitally controllable delay lines (202B, 204B) each include a plurality of delay elements (518_0 to 518_n, 520_0 to 520_n), and the time converter to numeric values (212) includes a corresponding second plurality of delay elements (512_0 to 512_n).
    [3" id="c-fr-0003]
    The digital delay lock loop according to claim 2, wherein each of the plurality of delay elements (508_0 to 508_n, 510_0 to 510_n) of the upstream portions is implemented by a circuit similar to that implementing each delay element of the first plurality (502_0 to 502_n), and each of the plurality of delay elements (518_0 to 518_nf 520_0 to 520_n) of the downstream portions is implemented by a circuit similar to that implementing each element of second plurality delay (512_0 to 512_n).
    [4" id="c-fr-0004]
    4. Digital delay lock loop according to any one of claims 1 to 3, in which the time converter into digital values further comprises a selector circuit (302) arranged to generate: a first pair of synchronization signals (UP_LEAD , DN_LAG) if the phase of the reference signal (TREF) precedes that of the delayed synchronization signal (TREF '), a first signal (UP_LEAD) of the first pair comprising a synchronization edge which advances a synchronization edge by a second signal (DN_LAG) of the first pair of said phase difference; and a second pair of synchronization signals (UP_LAG, DN_LEAD) if the phase of the reference signal (TREF) follows that of the delayed synchronization signal (TREF '), a first signal (DN_LEAD) of the second pair comprising a synchronization edge which precedes a synchronization edge of a second signal (UP_LAG) of the second pair of said phase difference.
    [5" id="c-fr-0005]
    The digital delay lock loop of claim 4, wherein the time to digital converter (212) comprises: an upstream time to digital converter (304) comprising a first delay line consisting of a first plurality delay elements (502_0 to 502_n) each having an output coupled to an input of a corresponding one of a first plurality of flip-flops (504_0 to 504_n), the first signal (UP_LEAD) of the first pair of synchronization signals being supplied to an input of the first delay line, and the first plurality of flip-flops receiving as clock the second signal (DN_LAG) of the first pair of synchronization signals; and a downstream time to digital converter (306) comprising a second delay line made up of a second plurality of delay elements (512_0 to 512_n) each having an output coupled to an input of a corresponding one second plurality of flip-flops (514_0 to 514_n), the first signal (DN_LEAD) of the second pair of synchronization signals being supplied to an input of the second delay line, and the second plurality of flip-flops receiving the second signal as a clock (UP_LAG ) of the second pair of synchronization signals.
    [6" id="c-fr-0006]
    6. Digital delay locking loop according to claim 5, in which: the first plurality of flip-flops (504_0 to 504_n) is arranged to generate a first digital signal (TLEAD_0 to TLEAD_n) represented by a thermometric code, the time converter to digital values (212) further comprising a first decoder (308) arranged to code the first digital signal based on one-hot coding; and the second plurality of flip-flops (514_0 to 514_n) is arranged to generate a second digital signal (TLAG_0 to TLAG_n) represented by a thermometric code, the time converter to digital values (212) further comprising a second decoder (310) arranged to code the second digital signal based on one-hot coding.
    [7" id="c-fr-0007]
    7. A digital delay lock loop according to any of claims 1 to 6, wherein the time converter to digital values further comprises an inverter to reverse the delayed synchronization signal.
    [8" id="c-fr-0008]
    8. A digital delay locked loop urn control method comprising: evaluating a phase difference between the reference signal (TREF) and a delayed synchronization signal (TREF ') generated by first and second controllable delay lines of digitally (202B, 204B) coupled in series with each other, each comprising an upstream portion (214, 218) and a downstream portion (216, 220), the first digitally controllable delay line receiving a reference synchronization signal ( TREF) and the second digitally controllable delay line providing a delayed synchronization signal (TREF '); generate a first control signal (DLEAD_ [0: n]) to control the upstream portions (214, 218) or a second control signal (DLAG [0: n]) to control the downstream portions (216, 220) on the basis of the sign and the amplitude of the phase difference.
    [9" id="c-fr-0009]
    9. The method as claimed in claim 8, further comprising the generation of: a first pair of synchronization signals (UP_LEAD, DN_LAG) if the phase of the reference signal (TREF) precedes that of the delayed synchronization signal (TREF '), first signal ion (UP_LEAD) of the first pair comprising a synchronization edge which precedes a synchronization edge of a second signal (DN_LAG) of the first pair of said phase difference; and a second pair of synchronization signals (UP_LAG, DN_LEAD) if the phase of the reference signal (TREF) follows that of the delayed synchronization signal (TREF '), a first signal (DN_LEAD) of the second pair comprising a synchronization edge which precedes a synchronization edge of a second signal (UP_LAG) of the second pair of said phase difference.
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    同族专利:
    公开号 | 公开日
    EP3506503B1|2021-07-14|
    EP3506503A1|2019-07-03|
    US10666270B2|2020-05-26|
    FR3076128B1|2021-09-10|
    US20190199361A1|2019-06-27|
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    法律状态:
    2018-12-31| PLFP| Fee payment|Year of fee payment: 2 |
    2019-06-28| PLSC| Publication of the preliminary search report|Effective date: 20190628 |
    2019-12-31| PLFP| Fee payment|Year of fee payment: 3 |
    2020-12-28| PLFP| Fee payment|Year of fee payment: 4 |
    2021-12-31| PLFP| Fee payment|Year of fee payment: 5 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1763220|2017-12-26|
    FR1763220A|FR3076128B1|2017-12-26|2017-12-26|DIGITAL DELAY LOCKING LOOP|FR1763220A| FR3076128B1|2017-12-26|2017-12-26|DIGITAL DELAY LOCKING LOOP|
    EP18214250.5A| EP3506503B1|2017-12-26|2018-12-19|Digital delay locked loop|
    US16/228,921| US10666270B2|2017-12-26|2018-12-21|Digital delay locked loop|
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